1. Field of the Invention
This invention relates to apparatus and methods for equalizing the bandwidth of multiple requesters utilizing a shared memory system.
2. Background of the Invention
Power consumption and cost reduction are key issues for storage devices such as tape drives. A typical storage device such as a tape drive is equipped with multiple processors that interface with external memory devices. In certain cases, the multiple processors share an external DRAM so that the number of DRAM chips can be reduced. Reducing the number of DRAM chips helps to reduce power consumption, cost, and the footprint of the circuit board. However, when using a shared memory system, storage device performance may be affected in two ways. First, the memory access turnaround times for the processors may be negatively affected. Second, memory sharing may provide unequal bandwidth to the processors.
When an access request from a processor is transmitted to an external DRAM, the turnaround time of the access request depends at least partly on the DRAM's protocol overhead. If a second access request is received from a second processor while the first access request is in process, the second processor must wait for the processing of the first access request to finish before processing of the second access request can begin. This increases the turnaround time for the second processor. In order to improve turnaround times in a shared memory system (such as a shared DDR3 SDRAM system), two different operating modes may be used—bank interleave mode (also referred to herein as “BI mode”) and continuous read/write mode (also referred to herein as “CN mode”).
When operating in BI mode, multiple banks of a DRAM may be open at the same time. A controller can send access requests to the multiple open banks in an interleaved manner without having to reopen the banks, thereby reducing turnaround times. Operation in CN mode allows a controller to submit multiple access requests (e.g., read and/or write commands) to the same bank and row as a previous access request without having to reopen the bank and row, thereby reducing overhead and improving turnaround times. Both the BI mode and CN mode improve DRAM bus efficiency, which in turn lowers the required clock frequency and power consumed.
Unlike personal computer or server systems, multiple processors in storage devices such as tape drives devices are not always intended to be used symmetrically. One processor may be designated as a primary processor while other processors are designated as secondary to or slaves of the primary processor. Secondary processors, for example, may perform ancillary tasks such as servo system and host interface tasks. As a result, an arbitration scheme is needed that provides priority to access requests from a primary processor.
However, giving priority to access requests from a primary processor can cause performance problems. For example, during a normal transfer (non-BI-mode transfer) where multiple access requests are received from multiple processors, the access request for the primary processor may be transferred to the shared memory system first. The access requests for the other non-primary processors may then be transferred to the shared memory system. The processor associated with the last access request (which may be a lower priority processor) may be allowed to operate in CN mode, which allows the processor to send multiple access requests with consecutive addresses to the shared memory system. This provides additional bandwidth to the last processor in the sequence. Unfortunately, this may also reduce the bandwidth of the primary processor or other processors, as well as increase their turnaround times.
In view of the foregoing, what are needed are apparatus and methods to equalize the bandwidth provided to multiple processors (or other requesters) submitting access requests to a shared memory system. Ideally, such apparatus and methods will equalize the average turnaround times for each of the processors (or other requesters) accessing the shared memory system.